Network List

Networklist can be used to map:

For the ATML demonstrations the UUT is built directly from common components resistors capacitors transistors etc. Describing these components is a edge use case for the ATML hardware descriptions. What is described below will be changed in future releases of the 'dot' standards and therefore replicating its use should be considered carefully.

Conceptually a NetworkList is a series on Networks, where each Network is a collection of nodes which are all joined together, where each is identified by an XPath (within the document) to an Port.

Walkthrough

In generating the NetworkList, for every set of pins, represented by their ports are connected together, a c:Network element is added with each c:Node representing each Port.

- <hc:NetworkList>
- <hc:Network>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/hc:Interface/c:Ports/c:Port[@name='DMM_MEAS']
</hc:Path>
  </hc:Node>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/te:Resources/hc:Resource[@name='DMM1'] /hc:Interface/c:Ports/c:Port[@name='MEAS']
</hc:Path>
  </hc:Node>
  </hc:Network>
- <hc:Network>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/hc:Interface/c:Ports/c:Port[@name='DMM_4W']
</hc:Path>
  </hc:Node>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/te:Resources/hc:Resource[@name='DMM1'] /hc:Interface/c:Ports/c:Port[@name='4Wire']
</hc:Path>
  </hc:Node>
  </hc:Network>
- <hc:Network>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/hc:Interface/c:Ports/c:Port[@name='DSO1_Channel1']
</hc:Path>
  </hc:Node>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/te:Resources/hc:Resource[@name='DSO1'] /hc:Interface/c:Ports/c:Port[@name='Channel1']
</hc:Path>
  </hc:Node>
  </hc:Network>
- <hc:Network>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/hc:Interface/c:Ports/c:Port[@name='PFG#1_ChannelA']
</hc:Path>
  </hc:Node>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/te:Resources/hc:Resource[@name='PFG#1'] /hc:Interface/c:Ports/c:Port[@name='Output']
</hc:Path>
  </hc:Node>
  </hc:Network>
- <hc:Network>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/hc:Interface/c:Ports/c:Port[@name='PFG#2_ChannelA']
</hc:Path>
  </hc:Node>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/te:Resources/hc:Resource[@name='PFG#2'] /hc:Interface/c:Ports/c:Port[@name='Output']
</hc:Path>
  </hc:Node>
  </hc:Network>
- <hc:Network>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/hc:Interface/c:Ports/c:Port[@name='SMU#1_Out1']
</hc:Path>
  </hc:Node>
- <hc:Node>
<hc:Path>
/ts:TestStationDescription/te:Resources/hc:Resource[@name='SMU#1'] /hc:Interface/c:Ports/c:Port[@name='Out1']
</hc:Path>
  </hc:Node>
  </hc:Network>
  </hc:NetworkList>