UUT Description

Standard

ATML IEEE standards

Source

Source documents

Analog UUT Description

The ATML Demo UUT has 'developed' over the lifetime of the project. Initially we all wanted to use a 'real' customer supplied UUT, but ran into the usual problems of availability, injecting faults to show diagnostics and having something we could run and share amongst all the team members. By having our own UUT design we've been able to add functionality such as RS232 busses and Digital control on top of an analogue design where we can inject known faults. The board represents an op-amp design with programmable gain which can be controlled through a parallel digital interface or RS232 bus and a RF amplifier. The UUT design, schematics and firmware were originally supplied by Ion Neag (Reston Software) and have been further developed by Remi Bedard (Spherea)

Name

Description

File
Schematic Revised schematic incorporating analogue, digital and RS232 but design, and connector interface Schematic_Hardware_diagram.pdf
Board layout ATML UUT board layout and dimensions PCB_Hardware_diagram.pdf

The specifications of the UUT card are listed below:

UUT Fault Insertion

The UUT design allows the board to simulate specific faults that could be used to show diagnostics, indictments and fault analysis. The design of the board is such that it has 9 fault insertion switches that provide the ability to simulate faults. The following table identifies the 'simulation' faults:

Switch and Position

Fault
SW5 OFF C2.OP/C1.OP
SW2 OFF R2.OP
SW10 OFF R1.OP
SW1 OFF Q1.B.OP
SW4 OFF R4.OP
SW6 OFF Q1.C.OP
SW7 OFF R3.OP
SW14 OFF C2.OP/C1.OP
SW3 ON Q1.CE.SR

UUT Tests

A set of measurements can be made on the UUT to test the correct operation of both amplifiers. These measurements are listed below:

The UUT design is such that on power-on the gain assumes a default value, equivalent to the digital components missing or not present; as was the case for the initial Phase I demonstration. In this default power-on state the following tests represent the simulated stimulus and response of the board.

Resistance Tests

Test Name

Signal

Ports

Instrument Precision

Limit
Vcc Resistance Test DC DSUB1-14 DSUB1-2 > 2.0 kOhm.
3.3V Resistance Test DC DSUB1-15 DSUB1-2 > 2.0 kOhm.
12V Resistance Test DC DSUB1-16 DSUB1-2 > 2.0 kOhm.

Apply DC Power

Test Name

Signal

Ports

Instrument Precision

Limit
Power supply 5 DC USB1 2% N/C

Voltage Test Procedure

Test Name

Signal

Ports

Instrument Precision

Limit
Vo AC Test Sinus AC DSUB1-3 DSUB1-2 > 500 mVpp
Vo DC Test DC DSUB1-3 DSUB1-2 < 0.1 V
Vo AC Test Sinus AC DSUB1-7 DSUB1-2 > 6 V and < 8 V
Vc DC Test DC DSUB1-7 DSUB1-2 < 0.15 V
Ve DC Test HIGH / LOW DC DSUB1-21 DSUB1-2 > 0.4 V and < 0.7 V
Vb DC Test HIGH / LOW DC DSUB1-22 DSUB1-2 > 1 V and < 12.5 V

RF Gain Tests

Action

Signal

Ports

Instrument Precision

Limit
RF Signal Generation RF Sinus -7dBm 0.5MHz U6 2%
Gain measurement RF Sinus 0.5MHz U7 >= 22 dB
RF Signal Generation RF Sinus -7dBm 1MHz U6 2%
Gain measurement RF Sinus 1MHz U7 >= 22 dB
RF Signal Generation RF Sinus -7dBm 1.5MHz U6 2%
Gain measurement RF Sinus 1.5MHz U7 >= 22 dB
RF Signal Generation RF Sinus -7dBm 2MHz U6 2%
Gain measurement RF Sinus 2MHz U7 >= 22 dB
RF Signal Generation RF Sinus -7dBm 2.5MHz U6 2%
Gain measurement RF Sinus 2.5MHz U7 >= 22 dB
RF Signal Generation RF Sinus -7dBm 3MHz U6 2%
Gain measurement RF Sinus 3MHz U7 >= 22 dB
RF Signal Generation RF Sinus -7dBm 3.5MHz U6 2%
Gain measurement RF Sinus 3.5MHz U7 >= 22 dB
RF Signal Generation RF Sinus -7dBm 4MHz U6 2%
Gain measurement RF Sinus 4MHz U7 >= 22 dB
RF Signal Generation RF Sinus -7dBm 4.5MHz U6 2%
Gain measurement RF Sinus 4.5MHz U7 >= 22 dB
RF Signal Generation RF Sinus -7dBm 5MHz U6 2%
Gain measurement RF Sinus 5MHz U7 >= 22 dB

RF Isolation Gain Tests

Action

Signal

Ports

Instrument Precision

Limit
RF Signal Generation RF Sinus -7dBm 0.5MHz U7 2%
Isolation measurement RF Sinus 0.5MHz U6 < -18 dB
RF Signal Generation RF Sinus -7dBm 1MHz U7 2%
Isolation measurement RF Sinus 1MHz U6 < -18 dB
RF Signal Generation RF Sinus -7dBm 1.5MHz U7 2%
Isolation measurement RF Sinus 1.5MHz U6 < -18 dB
RF Signal Generation RF Sinus -7dBm 2MHz U7 2%
Isolation measurement RF Sinus 2MHz U6 < -18 dB
RF Signal Generation RF Sinus -7dBm 2.5MHz U7 2%
Isolation measurement RF Sinus 2.5MHz U6 < -18 dB
RF Signal Generation RF Sinus -7dBm 3MHz U7 2%
Isolation measurement RF Sinus 3MHz U6 < -18 dB
RF Signal Generation RF Sinus -7dBm 3.5MHz U7 2%
Isolation measurement RF Sinus 3.5MHz U6 < -18 dB
RF Signal Generation RF Sinus -7dBm 4MHz U7 2%
Isolation measurement RF Sinus 4MHz U6 < -18 dB
RF Signal Generation RF Sinus -7dBm 4.5MHz U7 2%
Isolation measurement RF Sinus 4.5MHz U6 < -18 dB
RF Signal Generation RF Sinus -7dBm 5MHz U7 2%
Isolation measurement RF Sinus 5MHz U6 < -18 dB

RF P1dB Tests

Action

Signal

Ports

Instrument Precision

Limit
RF Signal Generation RF Sinus from 0.01 Vpp at 1MHz U6 2%
1 dB compression RF Sinus 1MHz U7 >= 10.5 dBm
RF Signal Generation RF Sinus from 0.01 Vpp at 2MHz U6 2%
1 dB compression RF Sinus 2MHz U7 >= 10.5 dBm
RF Signal Generation RF Sinus from 0.01 Vpp at 3MHz U6 2%
1 dB compression RF Sinus 3MHz U7 >= 10.5 dBm
RF Signal Generation RF Sinus from 0.01 Vpp at 4MHz U6 2%
1 dB compression RF Sinus 4MHz U7 >= 10.5 dBm
RF Signal Generation RF Sinus from 0.01 Vpp at 5MHz U6 2%
1 dB compression RF Sinus 5MHz U7 >= 10.5 dBm

ATML UUT Description

At this point (if you've opened all the links) you have all the information available on the UUT. The problem is that it’s all in propriety or user orientated format. It’s difficult to share this information electronically with another system without having to have significant user input in mapping the information. The purpose of the ATML UUT Description is to capture all this UUT information and allow the test information to be used and exchanged as part of the test system, without significant user interpretation.

The UUT Description described the 'hardware design' of the ATML Demo UUT board. The ATML UUT Description “ATMLDemo4(2017)_v1.xml” is a complete description of the UUT information. The example attempts to demonstrate all possible uses where ATML UUT Description could be used, in some cases pushing use-cases to the extreme limits of what can be supported.

Test Adaptor Description

One of the major components developed has been the Interface Test Adaptor (ITA) and Test Adaptor Description.