I. Analog UUT Description
The ATML Demo UUT has 'developed' over the lifetime of the project. Initially we all wanted to use a 'real' customer supplied UUT, but ran into the usual problems of availability, injecting faults to show diagnostics and having something we could run and share amongst all the team members. By having our own UUT design we've been able to add functionality such as RS232 busses and Digital control on top of an analogue design where we can inject known faults. The UUT design, schematics and firmware has been supplied by Ion Neag (Reston Software) and represents an op-amp design with programmable gain which can be controlled through a parallel digital interface or RS232 bus. The production board layout and screening has been supplied by GeoTest, who have provided the Gerber files and Bill Of Materials used as part of manufacturing the 6 demonstration UUTs.
|Schematic||Revised schematic incorporating analogue, digital and RS232 but design, and connector interface||ATML Demo III UUT.PDF|
|Board layout||ATML UUT board layout anddimensions||atml_demo_board.pdf|
The UUT design allows the board to simulate specific faults that could be used to show diagnostics, indictments and fault analysis. The design of the board is such that it has 10 (ten) fault insertion switches that provide the ability to simulate faults. The following table identifies the 'simulation' faults
Switch and Position
I.2. UUT Tests
The UUT design is such that on power-on the gain assumes a default value, equivalent to the digital components missing or not present; as was the case for the initial Phase I demonstration. In this default power-on state the following tests represent the simulated stimulus and response of the board.
|VCC Resistance Test||none||3.0 kΩ||13.2 kΩ|
|VO DC Voltage Test||VCC = 12V||VO, DC voltage||0.0 V||0.01 V|
|VI DC Voltage Test||VCC = 12V||VI, DC voltage||0.0 V||0.01 V|
|VO AC Voltage Test (VI Short)||VCC = 12V and VI - GND short||VO, TRMS||0.0 mV||10.0 mV|
|VO AC Voltage Test||VCC = 12V and VI = 4mVP-P @ 1KHz||VO, peak-to-peak||40 mVp-p||44 mVp-p|
|VC AC Voltage Test||VCC = 12V and VI = 4mVP-P @ 1KHz||VC, peak-to-peak||40 mVp-p||44 mVp-p|
|VC DC Voltage Test||VCC = 12V||VC, DC voltage||4.7 V||6.54 V||8 V|
|VE DC Voltage Test||VCC = 12V||VE, DC voltage||0.37 V||0.46 V||0.55 V|
|VB DC Voltage Test||VCC = 12V||VB, DC voltage||0.99 V||1.09 V||12.0 V|
I.3. ATML UUT Description
At this point (if you've opened all the links) you have all the information available on the UUT. The problem is that its all in propriety or user orientated format. Its difficult to share this information electronically with another system without having to have significant user input in mapping the information. The purpose of the ATML UUT Description is to capture all this UUT information and and allow the test information to be used and exchanged as part of the test system, without significant user interpretation.
The UUT Description described the 'hardware design' of the ATML Demo UUT board. The ATML UUT Description (UUTDescriptionDemo3.xml) is a complete description of the UUT information. The example attempts to demonstrate all possible uses where ATML UUT Description could be used, in some cases pushing use-cases to the extreme limits of what can be supported.
II. RF UUT Description
The UUT Description described the 'hardware design'
Compression and Gain test for Mini-Circuits ZJL-3G amplifier.
To determine the 1dB compression point of a unit under test, a suitable algorithm must be derived to traverse a range of input power levels; using the HI, LO and GO attributes of the ONE_DB_COMPRESSION_POINT TSF, until the 1dB compression point is found.
III. Test Adaptor Description
One of the major components developed through all three demonstrations has been the Interface Test Adaptor (ITA) and Test Adaptor Description.